— PCB/PWB
Footprint / Land Pattern Standards
IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard, defines land pattern geometry at three density levels — the same pad and courtyard shape, sized differently for the tradeoff between placement ease and board density:
| Density Level | Land Size | Typical Use |
|---|---|---|
| Level A — Most (Maximum) | Largest pads, most toe/heel/side fillet | Hand assembly/rework, low-volume prototypes |
| Level B — Nominal (Median) | Moderate pads | General-purpose production — the most common default |
| Level C — Least (Minimum) | Smallest pads, tightest fillet | High-density boards, fine-pitch parts |
Land pattern names encode package type, pitch, and lead count (e.g. SOIC127P600X175-8N) so a footprint can be identified from its name alone.
Trace Width vs. Current Capacity
The electrical equivalent of a load table — current capacity for 1 oz copper at a 10°C temperature rise, from the IPC-2221 empirical formula I = k·ΔT0.44·A0.725 (external k = 0.048, internal k = 0.024). See the PCB Trace Sizing calculator to solve for other copper weights, temperature rises, or currents.
| Trace Width | External Layer (1 oz, ΔT=10°C) | Internal Layer (1 oz, ΔT=10°C) |
|---|---|---|
| 10 mil (0.25 mm) | 0.89 A | 0.44 A |
| 20 mil (0.51 mm) | 1.46 A | 0.73 A |
| 40 mil (1.02 mm) | 2.42 A | 1.21 A |
| 100 mil (2.54 mm) | 4.70 A | 2.35 A |
| 200 mil (5.08 mm) | 7.77 A | 3.88 A |
Layer Stackups
| Layers | Typical Arrangement | Typical Use |
|---|---|---|
| 2 | Top signal / Bottom signal — no internal planes | Simple, low-speed, cost-sensitive designs |
| 4 | Signal / Ground / Power / Signal | Most common general-purpose board; planes give a short return path and shield the outer signals |
| 6 | Signal / Ground / Signal / Signal / Power / Signal | More routing layers plus dedicated planes for denser designs |
| 8+ | Multiple ground/power plane pairs interleaved with signal layers | High-speed/controlled-impedance designs needing tight plane coupling and isolation |
General principle: route signal layers directly adjacent to a reference plane (ground or power) — it controls impedance and keeps the return current's path short, which is the main lever for both signal integrity and EMI.
Via Types
| Type | Description |
|---|---|
| Through-hole via | Drilled and plated through the entire board; connects any layer to any other. Cheapest, most common. |
| Blind via | Connects an outer layer to one or more inner layers, without going through the whole board. |
| Buried via | Connects two or more inner layers only — invisible from either outer surface. |
| Microvia | Very small (typically <150µm), laser-drilled, usually a blind via between adjacent layers only. Used in HDI (High Density Interconnect) designs. |
See the Via Current Capacity calculator to size a via (or via array) for a given current.
Copper Weight
| Weight (oz/ft²) | Thickness (mil) | Thickness (µm) | Typical Use |
|---|---|---|---|
| 0.5 oz | 0.7 mil | 17.5 µm | Fine-pitch, high-density designs |
| 1 oz | 1.4 mil | 35 µm | Standard default for most PCBs |
| 2 oz | 2.8 mil | 70 µm | Higher-current designs |
| 3 oz | 4.2 mil | 105 µm | Power electronics |
| 4+ oz | 5.6+ mil | 140+ µm | High-current power boards |
Component Packages
SMD Chip Sizes (Resistors/Capacitors)
Named by length × width in hundredths of an inch (the metric code, in parentheses, is the same dimensions in tenths of a millimeter), per EIA-198.
| Imperial Code | Metric Code | Size (L × W) |
|---|---|---|
| 0201 | 0603 | 0.6 × 0.3 mm |
| 0402 | 1005 | 1.0 × 0.5 mm |
| 0603 | 1608 | 1.6 × 0.8 mm |
| 0805 | 2012 | 2.0 × 1.25 mm |
| 1206 | 3216 | 3.2 × 1.6 mm |